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ADDRESSABLE SIOX MEMORY ARRAY WITH INCORPORATED...

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    • Publication number: 20150162381
      Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxH, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.
      Type: Application
      Filed: August 27, 2012
      Publication date: June 11, 2015
      Applicants: Nanyang Technological University, William Marsh Rice University
      Inventors: James M. Tour, Jun Yao, Jian Lin, Gunuk Wang, Krishna Palem
    • Patent number: 9385163
      Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxH, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal to or greater than 1 and equal to or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.
      Type: Grant
      Filed: August 27, 2012
      Date of Patent: July 5, 2016
      Assignees: WILLIAM MARSH RICE UNIVERSITY, NANYANG TECHNOLOGICAL UNIVERSITY
      Inventors: James M. Tour, Jun Yao, Jian Lin, Gunuk Wang, Krishna Palem
    • Publication number: 20160276588
      Abstract: A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.
      Type: Application
      Filed: November 19, 2014
      Publication date: September 22, 2016
      Applicant: William Marsh Rice University
      Inventors: James M. Tour, Gunuk Wang, Yang Yang, Yongsung Ji
    • Publication number: 20160276411
      Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.
      Type: Application
      Filed: June 2, 2016
      Publication date: September 22, 2016
      Applicants: William Marsh Rice University
      Inventors: James M. Tour, Jun Yao, Jian Lin, Gunuk Wang, Krishna Palem
    • Publication number: 20130264536
      Abstract: Various embodiments of the present invention pertain to memresistor cells that comprise: (1) a substrate; (2) an electrical switch associated with the substrate; (3) an insulating layer; and (3) a resistive memory material. The resistive memory material is selected from the group consisting of SiOx, SiOxH, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. Additional embodiments of the present invention pertain to memresistor arrays that comprise: (1) a plurality of bit lines; (2) a plurality of word lines orthogonal to the bit lines; and (3) a plurality of said memresistor cells positioned between the word lines and the bit lines. Further embodiments of the present invention provide methods of making said memresistor cells and arrays.
      Type: Application
      Filed: September 8, 2011
      Publication date: October 10, 2013
      Applicants: Privatran, Inc., William Marsh Rice University
      Inventors: James M. Tour, Jun Yao, Burt Fowler, Glenn Mortland
    • Patent number: 9997705
      Abstract: A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.
      Type: Grant
      Filed: November 19, 2014
      Date of Patent: June 12, 2018
      Assignee: William Marsh Rice University
      Inventors: James M. Tour, Gunuk Wang, Yang Yang, Yongsung Ji
 
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